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| (Source: StatsChipPAC) |
Samsung Electronics and STATS ChipPAC have jointly filed three Korean patents, marking the first time the two companies have co-filed intellectual property together.
The jointly filed patents — "Semiconductor Package" (KR1020240001065), "Semiconductor Package and Fabricating Method Thereof" (KR1020240028151), and another "Semiconductor Package" (KR1020240029998) — were filed between January and February 2024 and published in May 2025.
The first patent (KR1020240001065) describes a semiconductor package structure featuring an upper package and a stiffener mounted on a printed circuit board (PCB). The stiffener is designed to contact the PCB along its edges while remaining spaced apart at the center, helping to reduce warpage, relieve mechanical stress from thermal expansion, and enhance overall structural reliability. Its openings are vertically aligned with the upper package to optimize cooling and heat dissipation paths in high-density packages.
Applications include high-performance packages requiring structural rigidity, such as server CPUs, GPUs, AI accelerators, and multi-chip packages (MCPs).
The second patent (KR1020240028151) relates to a package structure in which a semiconductor chip is mounted on an interposer. Between the interposer and the chip are UBM (Under Bump Metallization) pads and connecting members that contact the sides of the UBM pads, reducing electrical resistance and improving mechanical strength and thermal durability. The design supports ultra-fine-pitch bump structures, making it suitable for next-generation 2.5D/3D and HBM stacking packages.
Potential applications include HBM interposer-based packages, SoC + HBM integrated modules, and AI/HPC interposer assemblies.
The third patent (KR1020240029998) covers a semiconductor package featuring a stiffener with multiple rectangular openings, each accommodating one or more semiconductor chips. The configuration minimizes chip-to-chip interference and enhances thermal distribution and multi-chip alignment efficiency. The stiffener also reinforces the substrate mechanically, preventing warpage in large-area packages and maintaining stability under high-temperature operating conditions.
Applications include multi-chip packages (MCPs), chiplet-based 2.5D packages, large server chip modules, and AI/data center packaging systems requiring efficient multi-chip layouts.
All three patents fall within the domain of advanced semiconductor packaging technology, improving substrate rigidity, interconnect reliability, and thermal management in high-power, high-density environments such as AI accelerators, HPC processors, and HBM memory packages.
By PatenTrip
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