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| (Source: Kovis Technology) |
SK Hynix and Kovis Technology, a South Korean semiconductor equipment company, have jointly filed two Korean patents related to automated semiconductor inspection systems, marking their first known collaboration in the field.
The first patent, titled "Automatic Thermal Warpage Characteristic Analysis Apparatus for Semiconductor Package Using Thermal Image and Method Thereof" (KR1020230017324), was filed in February 2023 and published in August 2024.
The second, "Semiconductor Surface Contamination Inspection Device Using Multiple Potential Difference Sensors" (KR1020240010267), was filed in January 2024 and published in July 2025, according to the Korean Intellectual Property Office.
The '324 patent discloses a system that automatically measures and analyzes the thermal warpage characteristics of BGA IC semiconductor packages using thermal imaging and 3D optical technology.
Traditional methods required multiple manual steps — such as removing solder balls, applying white spray paint, and manually attaching thermocouples — before testing. In contrast, the new system enables fully automated measurement through a single workflow: Tray loading → robotic alignment → thermal heating → 3D optical analysis.
By simply loading a tray of chips, the system automatically evaluates the thermal deformation of IC packages without manual preparation, improving productivity and test consistency. A Cartesian (XY) robot automatically transfers and aligns IC chips between the tray and the oven, eliminating human intervention. The inclusion of multiple DFP Moiré (Digital Fringe Projection) modules allows simultaneous large-area scanning while maintaining Z-axis resolution and measurement precision, combining both speed and accuracy in thermal analysis.
The '267 patent describes a non-contact inspection device that uses multiple potential-difference sensors to evaluate surface contamination and non-uniformity on semiconductor wafers.
The system mounts wafers on a precision granite base, where a motorized wafer holder rotates the sample. A gantry structure equipped with two or more potential-difference sensors scans across the wafer surface to detect surface charge variations and contamination levels without physical contact. The resulting signals are analyzed by a control unit, which identifies defective or contaminated wafers automatically.
The '267 patent was developed under a national R&D project funded by South Korea's Ministry of Trade, Industry and Energy (MOTIE). The program, managed by the Korea Evaluation Institute of Industrial Technology (KEIT), was conducted as part of the "Machinery and Equipment Industry Technology Development Program / Manufacturing-Based Production Systems."
The specific project, titled "Development of a Combined Measurement System for High-Precision Mass Measurement and Surface Contamination Defect Inspection of Semiconductor Wafers," has been carried out by Kovis Technology since April 2023 and is scheduled to conclude in December 2025.
By PatenTrip
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