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| (Source: TSMC) |
TSMC has acquired 11 U.S. semiconductor packaging patents from individual inventor Cheng-Wei Wu in July, marking the first time the chipmaker has purchased patents from him.
Eight of the patents are granted and three have been abandoned.
The portfolio covers structural innovations in advanced packaging aimed at enhancing electrical performance, reliability and manufacturing efficiency through redistribution layer (RDL) design, die placement, interconnect post geometry and multi-via configurations. These include bump-less die-to-RDL connections, curved-sidewall interconnect posts, and differentiated RDL trace thicknesses across layers.
According to the patents, the RDL-related inventions use multiple metallization layers with varying trace thicknesses — such as thinner traces in the first layer and thicker ones in the upper layers — to optimize electrical characteristics and ease fabrication, while improving interconnect efficiency and signal integrity.
The bump-less connection designs directly bond first and second dies to the RDL without solder bumps, with the dies laterally offset in top view to improve integration density and design flexibility.
In the interconnect post innovations, the posts feature wider top and bottom ends and a narrower waist to improve mechanical stability and connection reliability. The sidewalls are inwardly or outwardly curved to distribute stress and enhance electrical and thermal performance.
The multi-via placement technology clusters vias within a defined “via zone” directly beneath a conductive unit’s vertical footprint, reducing contact resistance, improving signal quality and maximizing space efficiency.
Below are the titles and abstracts of the individual patents, listed by application number with corresponding registration numbers in parentheses.
Application No. 14/952,920 (Abandoned) — “Semiconductor Package.”
-Discloses a package with a die, a redistribution structure and multiple metal posts. The RDL includes three sublayers with varying metal trace thicknesses, where the first layer’s traces are thinner than those in the third layer.
Application No. 15/253,011 (U.S. Patent No. 9,679,872) — “Connection Structure for Semiconductor Package Having Plural Vias Located Within Projection of Conductive Unit.”
-Describes a conductive unit in direct contact with a solder bump, layered insulating structures, and a via zone located within the vertical projection of the conductive unit to reduce resistance and improve signal quality.
Application No. 15/403,409 (U.S. Patent No. 9,887,176) — “Semiconductor Package.”
-Covers a package with first and second dies directly connected to the RDL without solder bumps, positioned with a lateral offset in top view to optimize layout.
Application No. 15/676,019 (U.S. Patent No. 10,283,467) — “Semiconductor Package.”
-Discloses a metal post with wider top and bottom ends, a narrower waist, and curved sidewalls to improve stability, reliability and stress distribution.
Application No. 15/850,403 (U.S. Patent No. 10,269,765) — “Semiconductor Package.”
-Similar to U.S. Patent No. 9,887,176, detailing bump-less die-to-RDL connections with laterally offset dies.
Application No. 16/118,710 (U.S. Patent No. 10,541,217) — “Semiconductor Package.”
-Similar to U.S. Patent No. 10,283,467, describing a metal post with a narrowed waist and curved sidewalls.
Application No. 16/298,173 (U.S. Patent No. 10,600,757) — “Semiconductor Package.”
-Similar to U.S. Patent No. 9,887,176, covering laterally offset dies connected to the RDL without solder bumps.
Application No. 16/705,751 (U.S. Patent No. 10,957,662) — “Semiconductor Package.”
-Similar to U.S. Patent No. 10,283,467, with metal post geometry designed for improved reliability and stress control.
Application No. 16/804,452 (Abandoned) — “Semiconductor Package.”
-Similar to U.S. Patent No. 9,887,176, with laterally offset dies and bump-less connections.
Application No. 17/176,574 (U.S. Patent No. 11,658,137) — “Semiconductor Package.”
-Similar to U.S. Patent No. 10,283,467, disclosing metal posts with a narrowed waist and curved sidewalls.
Application No. 18/078,383 (Abandoned) — “Semiconductor Package.”
-Similar to U.S. Patent No. 10,283,467, with curved-sidewall metal posts and narrowed waist for enhanced mechanical performance.
By PatenTrip
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