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| (Source: Idemitsu) |
Idemitsu Kosan has entered into an agreement with Japan Display Inc. (JDI) to share rights to 30 pending U.S. patent applications covering oxide semiconductor technology. This marks the first time the Japanese energy and materials company has obtained rights from the display panel maker.
According to the U.S. Patent and Trademark Office, Japan Display agreed to grant Idemitsu co-ownership in the applications, all of which remain at the application stage.
The portfolio centers on polycrystalline oxide thin-film transistor (TFT) technology — specifically IGZO (indium gallium zinc oxide) devices — and manufacturing methods for use in display backplanes. The inventions detail semiconductor device structures incorporating oxide semiconductor layers with tailored crystal structures, controlled impurity concentrations, and buffer layers such as aluminum oxide. They also disclose processing conditions, including sputter deposition, oxygen partial pressure control, crystallization annealing, and etching resistance improvements using phosphoric acid-based solutions, to achieve high mobility and low leakage characteristics.
Several applications describe integration of these polycrystalline oxide TFTs into display panels, including configurations where sensor elements are embedded behind the display area. Others focus on structural variations — such as multi-region oxide layers with differing electrical properties, dual-gate architectures, and specific contact hole arrangements — to enhance performance, reliability and manufacturability for high-resolution, high-refresh-rate displays.
Below is a list of the 30 U.S. patents Japan Display has shared rights to with Idemitsu Kosan.
Patent Application Invention title
None 18230171 DISPLAY DEVICE
None 18346280 SEMICONDUCTOR DEVICE
None 18411028 SEMICONDUCTOR DEVICE
None 18895446 DISPLAY DEVICE
None 18895467 SEMICONDUCTOR DEVICE
None 18895479 SEMICONDUCTOR DEVICE
None 18897024 SEMICONDUCTOR DEVICE
None 18335447 SEMICONDUCTOR DEVICE
None 18474389 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
None 18519392 SEMICONDUCTOR DEVICE
None 18597186 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
None 18604840 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
None 18617858 SEMICONDUCTOR DEVICE AND DISPLAY DEVICE
None 18618022 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
None 18651909 SEMICONDUCTOR DEVICE
None 18656855 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
None 18760532 SEMICONDUCTOR DEVICE AND DISPLAY DEVICE
None 18887079 SEMICONDUCTOR DEVICE
None 18887091 SEMICONDUCTOR DEVICE
None 18887167 SEMICONDUCTOR DEVICE
None 18890900 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
None 18894340 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
None 18895591 SEMICONDUCTOR DEVICE
None 18897128 SEMICONDUCTOR DEVICE
None 18898825 SEMICONDUCTOR DEVICE
None 18898827 SEMICONDUCTOR DEVICE
None 18898831 SEMICONDUCTOR DEVICE
None 18934397 SEMICONDUCTOR DEVICE
None 18934519 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
None 18960197 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Below are the application numbers and corresponding abstracts for the 30 U.S. patents for which Japan Display has shared rights with Idemitsu Kosan.
18230171
A display device includes a display panel including a display portion having a plurality of pixels; and a sensor element disposed on a rear side of the display portion. The display portion has a first region overlapping the sensor element and a second region other than the first region in a plan view. Each of the plurality of pixels has a semiconductor device including a channel portion and a conductive portion made of an oxide semiconductor having a polycrystalline structure. Each of the plurality of pixels in the first region is connected by a first signal line comprising the same layer as the conductive portion, and each of the plurality of pixels in the second region is connected by a second signal line comprising a metal layer connected to the conductive portion.
18346280
A semiconductor device includes a oxide semiconductor layer provided on an insulating surface and having a channel area, a source area and a drain area sandwiching the channel area, a gate electrode opposite the channel area, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, wherein the gate electrode is an oxide conductive layer having the same composition as the oxide semiconductor layer, and the oxide conductive layer includes the same impurity element as the source area and the drain area.
18411028
A semiconductor device includes an oxide semiconductor layer including a polycrystalline structure, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first transparent conductive layer connected to the oxide semiconductor layer, and a second transparent conductive layer arranged in the same layer as the first transparent conductive layer and separated from the first transparent conductive layer, wherein crystallizability of the first transparent conductive layer is different from crystallizability of the second transparent conductive layer.
18895446
A display device includes a light-emitting element, a first transistor, and a second transistor, the first transistor includes a first gate electrode, a first insulating film, a first oxide semiconductor layer, a second insulating film, and a first conductive layer provided on the second insulating film, and the second transistor includes the first insulating film, a second oxide semiconductor layer, a second insulating film, and a second gate electrode, wherein an etching rate of the first oxide semiconductor layer and the second semiconductor layer is less than 3 nm/min when the first oxide semiconductor layer and the second semiconductor layer are etched using an etching solution containing phosphoric acid as a main component at 40° C.
18895467
A semiconductor device includes a light shielding layer, a first silicon nitride insulating layer in contact with the light shielding layer with a first interface, a first silicon oxide insulating layer in contact with the first silicon nitride layer with a second interface, and an oxide semiconductor layer over the first silicon oxide insulating layer. The first silicon oxide insulating layer is in contact with the second silicon oxide insulating layer. A thickness t of the first silicon nitride layer satisfies a condition in which light reflected at the first interface and light reflected at the second interface weaken each other when light having a wavelength of 450 nm is incident on the first silicon nitride insulating layer at an angle of 60 degrees from a normal direction of the second interface.
18895479
A semiconductor device according to an embodiment of the present invention includes an oxide semiconductor layer having a polycrystalline structure and including an impurity region containing an impurity element, a gate electrode over the oxide semiconductor layer, an insulating layer between the oxide semiconductor layer and the gate electrode, a first contact hole penetrating the insulating layer and exposing the impurity region, a second contact hole penetrating at least the insulating layer and having a greater depth than the first contact hole, and a connection wiring electrically connecting the impurity region to a layer which is exposed in the second contact hole through the first contact hole and the second contact hole. The connection wiring includes a first conductive layer and a second conductive layer on the first conductive layer. A portion of the first conductive layer that is exposed from the second conductive layer contains the impurity element.
18897024
A semiconductor device includes a gate electrode, an oxide semiconductor layer having a polycrystalline structure, and a gate insulating layer between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes a source region and a drain region each containing an impurity element, a channel region between the source region and the drain region, and a first region adjacent to the channel region. The first region includes a first edge extending along a first direction travelling from the source region to the drain region. The first region has a higher electrical resistivity than each of the source region and the drain region. An etching rate of the oxide semiconductor layer is less than 3 nm/min when the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at 40° C.
18335447
A semiconductor device includes an oxide semiconductor layer having a polycrystalline structure on an insulating surface, a gate electrode over the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The oxide semiconductor layer includes a first region having a first crystal structure overlapping the gate electrode and a second region having a second crystal structure not overlapping the gate electrode. An electrical conductivity of the second region is larger than an electrical conductivity of the first region. The second crystal structure is identical to the first crystal structure.
18474389
A method for manufacturing a semiconductor device includes depositing a first metal oxide film with aluminum as a major component on a substrate, depositing an amorphous oxide semiconductor film on the first metal oxide film under an oxygen partial pressure of 3% to 5%, processing the oxide semiconductor film into a patterned oxide semiconductor layer, crystallizing the oxide semiconductor layer by performing a first heat treatment on the patterned oxide semiconductor layer, processing the first metal oxide film using the crystallized oxide semiconductor layer as a mask, depositing a gate insulating film on the oxide semiconductor layer, and forming a gate electrode on the gate insulating film, wherein a thickness of the oxide semiconductor film is more than 10 nm and 30 nm or less.
18519392
A semiconductor device includes an oxide insulating layer, an oxide semiconductor layer on the oxide insulating layer, a gate insulating layer on and in contact with the oxide semiconductor layer, and a gate electrode on the gate insulating layer. The oxide semiconductor layer includes a channel region overlapping the gate electrode, and source and drain regions that do not overlap the gate electrode. At an interface between the source and drain regions and the gate insulating layer, a concentration of an impurity on a surface of at least one of the source and drain regions is greater than or equal to 1×1019 cm−3.
18597186
A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer having a polycrystalline structure over the gate insulating layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer. The interlayer insulating layer covers the source electrode and the drain electrode. The oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer. A difference between a film thickness of the first region and a film thickness of the second region is less than or equal to 5 nm.
18604840
A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, a metal oxide layer over the gate insulating layer, an oxide semiconductor layer having a polycrystalline structure over the metal oxide layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer, the interlayer insulating layer covering the source electrode and the drain electrode, wherein the oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer, and a difference between a thickness of the first region and a thickness of the second region is 5 nm or less.
18617858
A semiconductor device comprises a first insulating layer; a metal oxide layer mainly composed of aluminum on the first insulating layer; an oxide semiconductor layer having a polycrystalline structure on the metal oxide layer; a gate insulating layer on the oxide semiconductor layer; a gate electrode on the gate insulating layer; and a second insulating layer on the gate electrode. The metal oxide layer and the oxide semiconductor layer are both patterned, and the oxide semiconductor layer has a first region in contact with the gate insulating layer and a second region continuous with the first region in a first direction and in contact with the gate insulating layer and the second insulating layer.
18618022
A semiconductor device comprises a metal oxide layer on an insulating surface; an oxide semiconductor layer on the metal oxide layer; a gate insulating layer on the oxide semiconductor layer; and a gate wiring on the gate insulating layer. The metal oxide layer has a first region overlapping the gate wiring and the oxide semiconductor layer, a second region overlapping the oxide semiconductor layer and not overlapping the gate wiring, and a third region overlapping the gate wiring and not overlapping the oxide semiconductor layer.
18651909
A semiconductor device according to an embodiment of the present invention includes: a gate electrode; a gate insulating layer; a metal oxide layer containing aluminum as a main component above the gate insulating layer; an oxide semiconductor layer having a polycrystalline structure above the metal oxide layer; a source electrode and a drain electrode contacting the oxide semiconductor layer from above the oxide semiconductor layer; and an insulating layer above the source electrode and the drain electrode, wherein a linear mobility of the semiconductor device is larger than 20 cm2/Vs when (Vg−Vth)×Cox=5×10−7 C/cm2, in the case where the Vg is a voltage supplied to the gate electrode, the Vth is a threshold voltage of the semiconductor device, and the Cox is an electrostatic capacitance of the gate insulating layer sandwiched by the gate electrode and the oxide semiconductor layer.
18656855
A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer having a polycrystalline structure over the gate insulating layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer, the interlayer insulating layer covering the source electrode and the drain electrode. The oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer. A difference between a thickness of the first region and a thickness of the second region is less than or equal to 1 nm.
18760532
A semiconductor device comprises a first insulating layer, an oxide semiconductor layer having a polycrystalline structure on the first insulating layer, a gate insulating layer on the oxide semiconductor layer, a gate wiring on the gate insulating layer, and a second insulating layer on the gate wiring. The oxide semiconductor layer has a first region, a second region and a third region aligned toward a first direction. The first region overlaps the gate insulating layer and the gate wiring. The third region is in contact with the second insulating layer. A distance from a top surface of the second region to a top surface of the second insulating layer is longer than a distance from a top surface of the third region to the top surface of the second insulating layer.
18887079
A semiconductor device includes a first gate electrode, an oxide semiconductor layer including a first oxide semiconductor having a polycrystalline structure over the first gate electrode, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, and a second gate electrode overlapping the first gate electrode and the oxide semiconductor layer over the source electrode and the drain electrode. In a plan view, the second gate electrode is located with a space from each of the source electrode and the drain electrode. The second gate electrode is electrically connected to the first gate electrode.
18887091
A semiconductor device comprises a first insulating layer; an oxide semiconductor layer having a polycrystalline structure on the first insulating layer; a gate insulating layer on the semiconductor oxide layer; a buffer layer on the gate insulating layer; a gate wiring on the buffer layer; and a second insulating layer on the gate wiring. The oxide semiconductor layer has a first region, a second region and a third region aligned toward a first direction. An electrical resistivity of the second region is higher than an electrical resistivity of the first region and lower than an electrical resistivity of the third region. A sheet resistance of the third region is less than 1000 ohm/square.
18887167
A semiconductor device according to an embodiment of the present invention includes: a first semiconductor layer; a first gate electrode; a first gate insulating layer; a first insulating layer above the first gate electrode; a first electrode overlapping the first semiconductor layer, and electrically connected to the first semiconductor layer; a second semiconductor layer above the first insulating layer and made of a different material from the first semiconductor layer; a second gate electrode; a second gate insulating layer; a second electrode overlapping the second semiconductor layer, and electrically connected to the second semiconductor layer; and a first metal nitride layer between the second semiconductor layer and the second electrode, wherein the second semiconductor layer is polycrystalline, and an etching rate of the second semiconductor layer with respect to an etchant including phosphoric acid as a main component is less than 3 nm/min at 40° C.
18890900
A semiconductor device includes a first gate electrode, an oxide semiconductor layer including a first oxide semiconductor having a polycrystalline structure over the first gate electrode, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, and a second gate electrode overlapping the first gate electrode and the oxide semiconductor layer over the source electrode and the drain electrode. The second gate electrode includes a second oxide semiconductor having a polycrystalline structure. The second gate electrode is electrically connected to the first gate electrode.
18894340
A method for manufacturing a semiconductor device, the method comprising steps of: forming a first metal oxide layer containing aluminium as a main component above an insulating surface; performing a planarization process on a surface of the first metal oxide layer; forming an oxide semiconductor layer on the insulating surface on which the planarization process is performed; forming a gate insulating layer above the oxide semiconductor layer; and forming a gate electrode facing the oxide semiconductor layer above the gate insulating layer.
18895591
A semiconductor device according to an embodiment of the present invention includes: an oxide semiconductor layer; a first gate electrode facing the oxide semiconductor layer; a first gate insulating layer between the oxide semiconductor layer and the first gate electrode; an electrode arranged in a region overlapping the oxide semiconductor layer in a plan view and electrically connected to the oxide semiconductor layer; and a metal nitride layer between the oxide semiconductor layer and the electrode, wherein the oxide semiconductor layer is polycrystalline, and an etching rate of the oxide semiconductor layer with respect to an etchant containing phosphoric acid as a main component is less than 3 nm/min at 40° C.
18897128
A semiconductor device according to an embodiment includes an oxide semiconductor layer provided above an insulating surface, a gate insulating layer provided above the oxide semiconductor layer, and a gate electrode provided above the oxide semiconductor layer via the gate insulating layer, wherein the gate electrode has a titanium-containing layer and a conductive layer in order from the gate insulating layer side, the gate insulating layer includes a first region overlapping the gate electrode and a second region not overlapping the gate electrode, and a thickness of the titanium-containing layer is 50% or less than a thickness of the gate insulating layer in the first region.
18898825
A semiconductor device includes a substrate, an insulating layer over the substrate, a metal oxide layer over the insulating layer, and an oxide semiconductor layer over the metal oxide layer. The insulating layer includes a first region overlapping the metal oxide layer and a second region not overlapping the metal oxide layer. A hydrogen concentration of the first region is greater than a hydrogen concentration of the second region. A nitrogen concentration of the first region is greater than a nitrogen concentration of the second region.
18898827
A semiconductor device according to an embodiment includes: a metal oxide layer above a substrate, the metal oxide layer containing aluminum as a main component; an oxide semiconductor layer above the metal oxide layer; a gate electrode facing the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein the oxide semiconductor layer includes two or more metals including indium, and a ratio of indium in the two or more metals is 50% or more.
18898831
A semiconductor device includes a metal oxide layer over an insulating surface and an oxide semiconductor layer over the metal oxide layer. A fluorine concentration of the metal oxide semiconductor layer is greater than or equal to 1×1018 atoms/cm3. In a SIMS analysis, a secondary ion intensity of fluorine detected in the metal oxide layer may be greater than or equal to 10 times a secondary ion intensity of fluorine detected in the oxide semiconductor layer.
18934397
A semiconductor device includes a metal oxide layer containing aluminum over an insulating surface and an oxide semiconductor layer over the metal oxide layer. The oxide semiconductor layer includes a first crystal region in contact with the metal oxide layer and a second crystal region in contact with the first crystal region and having a larger area than the first crystal region in a cross-sectional view of the oxide semiconductor layer. The first crystal region and the second crystal region differ from each other in at least one of a crystal structure and a crystal orientation.
18934519
A method for manufacturing a semiconductor device comprises steps of: forming an oxide semiconductor layer on a substrate by a sputtering method; performing a first heat treatment on the oxide semiconductor layer after placing the substrate on which the oxide semiconductor layer is formed in a heating furnace having a heating medium maintained at a preset temperature; forming a gate insulating layer on the oxide semiconductor layer after the first heat treatment; and forming a gate electrode on the gate insulating layer. When the substrate is installed in the heating furnace, a temperature drop of the heating medium is kept within 15% of the set temperature.
18960197
A semiconductor device includes a metal oxide layer containing aluminum as a main component above an insulating surface, an oxide semiconductor layer on the metal oxide layer; a gate electrode facing the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein a water contact angle on an upper surface of the metal oxide layer is 20° or lower.
By PatenTrip
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