AMD Transfers Patents in November 2024
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| (Source: https://www.amd.com/en/newsroom/press-releases/2025-1-14-amd-to-report-fiscal-fourth-quarter-and-full-year-.html) |
By PatenTrip
Advanced Micro Devices, Inc. (AMD) transferred 122 U.S. patents to Onesta IP in a transaction completed in November 2024.
The transferred patents span multiple technology sectors, including semiconductor manufacturing and packaging, computing architecture and processor design, GPU and graphics processing, memory and storage, interface and I/O technologies, as well as AI and neural network computing.
While Onesta IP has yet to initiate any patent litigation, its acquisition of AMD's patents follows a pattern observed in other transactions involving the chipmaker.
AMD has previously assigned patents to entities such as Fullbrite Capital Partners and Innovative Foundry Technologies LLC (IFT). Notably, IFT filed patent infringement lawsuits in 2019 against Qualcomm, Broadcom, TSMC, SMIC, TCL, and Hisense in the United States.
The implications of Onesta IP's latest patent acquisition remain unclear, but the transaction underscores the ongoing monetization and reallocation of intellectual property within the semiconductor industry.
The list of patents AMD transferred to Onesta IP is as follows:
Patent Application Invention title
8497162 11379741 Lid Attach Process
7774578 11448337 APPARATUS AND METHOD OF PREFETCHING DATA IN RESPONSE TO A CACHE MISS
7774578 11448337 APPARATUS AND METHOD OF PREFETCHING DATA IN RESPONSE TO A CACHE MISS
7717350 11478740 PORTABLE COMPUTING PLATFORM HAVING MULTIPLE OPERATING MODES AND HETEROGENEOUS PROCESSORS
7717350 11478740 PORTABLE COMPUTING PLATFORM HAVING MULTIPLE OPERATING MODES AND HETEROGENEOUS PROCESSORS
7517782 11536041 METHOD OF FORMING A METAL LAYER OVER A PATTERNED DIELECTRIC BY WET CHEMICAL DEPOSITION INCLUDING AN ELECTROLESS AND A POWERED PHASE
7517782 11536041 METHOD OF FORMING A METAL LAYER OVER A PATTERNED DIELECTRIC BY WET CHEMICAL DEPOSITION INCLUDING AN ELECTROLESS AND A POWERED PHASE
7723195 11566287 METHOD OF FORMING A FIELD EFFECT TRANSISTOR
7723195 11566287 METHOD OF FORMING A FIELD EFFECT TRANSISTOR
7996731 11592074 ERROR DETECTION IN HIGH-SPEED ASYMMETRIC INTERFACES
7996731 11592074 ERROR DETECTION IN HIGH-SPEED ASYMMETRIC INTERFACES
8892963 11595619 Error detection in high-speed asymmetric interfaces utilizing dedicated interface lines
8892963 11595619 Error detection in high-speed asymmetric interfaces utilizing dedicated interface lines
7725690 11674562 DISTRIBUTED DISPATCH WITH CONCURRENT, OUT-OF-ORDER DISPATCH
7725690 11674562 DISTRIBUTED DISPATCH WITH CONCURRENT, OUT-OF-ORDER DISPATCH
7734873 11754589 CACHING OF MICROCODE EMULATION MEMORY
7734873 11754589 CACHING OF MICROCODE EMULATION MEMORY
8173538 11757022 METHOD OF SELECTIVELY FORMING A CONDUCTIVE BARRIER LAYER BY ALD
8173538 11757022 METHOD OF SELECTIVELY FORMING A CONDUCTIVE BARRIER LAYER BY ALD
7678615 11846618 SEMICONDUCTOR DEVICE WITH GEL-TYPE THERMAL INTERFACE MATERIAL
7678615 11846618 SEMICONDUCTOR DEVICE WITH GEL-TYPE THERMAL INTERFACE MATERIAL
7861041 11849515 SECOND CHANCE REPLACEMENT MECHANISM FOR A HIGHLY ASSOCIATIVE CACHE MEMORY OF A PROCESSOR
7861041 11849515 SECOND CHANCE REPLACEMENT MECHANISM FOR A HIGHLY ASSOCIATIVE CACHE MEMORY OF A PROCESSOR
8357268 11861689 SYSTEM FOR DRIVING AND CONTROLLING A MOVABLE ELECTRODE ASSEMBLY IN AN ELECTROCHEMICAL PROCESS TOOL
8357268 11861689 SYSTEM FOR DRIVING AND CONTROLLING A MOVABLE ELECTRODE ASSEMBLY IN AN ELECTROCHEMICAL PROCESS TOOL
7943442 11862296 SOI DEVICE HAVING A SUBSTRATE DIODE WITH PROCESS TOLERANT CONFIGURATION AND METHOD OF FORMING THE SOI DEVICE
7943442 11862296 SOI DEVICE HAVING A SUBSTRATE DIODE WITH PROCESS TOLERANT CONFIGURATION AND METHOD OF FORMING THE SOI DEVICE
None 11960640 Video Data Capture and Streaming
8502832 12130364 FLOATING POINT TEXTURE FILTERING USING UNSIGNED LINEAR INTERPOLATORS AND BLOCK NORMALIZATIONS
8502832 12130364 FLOATING POINT TEXTURE FILTERING USING UNSIGNED LINEAR INTERPOLATORS AND BLOCK NORMALIZATIONS
8861591 12189060 Software Video Encoder with GPU Acceleration
8861591 12189060 Software Video Encoder with GPU Acceleration
8233527 12264892 SOFTWARE VIDEO TRANSCODER WITH GPU ACCELERATION
8233527 12264892 SOFTWARE VIDEO TRANSCODER WITH GPU ACCELERATION
7659768 12339800 REDUCED LEAKAGE VOLTAGE LEVEL SHIFTING CIRCUIT
9006114 12359839 METHOD FOR SELECTIVELY REMOVING A SPACER IN A DUAL STRESS LINER APPROACH
9006114 12359839 METHOD FOR SELECTIVELY REMOVING A SPACER IN A DUAL STRESS LINER APPROACH
8402075 12404426 MECHANISM FOR FAST DETECTION OF OVERSHIFT IN A FLOATING POINT UNIT OF A PROCESSING DEVICE
8402075 12404426 MECHANISM FOR FAST DETECTION OF OVERSHIFT IN A FLOATING POINT UNIT OF A PROCESSING DEVICE
None 12476152 Unified Shader Engine Filtering System
9093040 12476158 REDUNDANCY METHOD AND APPARATUS FOR SHADER COLUMN REPAIR
9093040 12476158 REDUNDANCY METHOD AND APPARATUS FOR SHADER COLUMN REPAIR
8195882 12476159 SHADER COMPLEX WITH DISTRIBUTED LEVEL ONE CACHE SYSTEM AND CENTRALIZED LEVEL TWO CACHE
8195882 12476159 SHADER COMPLEX WITH DISTRIBUTED LEVEL ONE CACHE SYSTEM AND CENTRALIZED LEVEL TWO CACHE
8558836 12476161 Scalable and Unified Compute System
8558836 12476161 Scalable and Unified Compute System
None 12476202 Multi Instance Unified Shader Engine Filtering System With Level One and Level Two Cache
None 12508902 DETERMINING PERFORMANCE SENSITIVITIES OF COMPUTATIONAL UNITS
8447994 12508929 ALTERING PERFORMANCE OF COMPUTATIONAL UNITS HETEROGENEOUSLY ACCORDING TO PERFORMANCE SENSITIVITY
8447994 12508929 ALTERING PERFORMANCE OF COMPUTATIONAL UNITS HETEROGENEOUSLY ACCORDING TO PERFORMANCE SENSITIVITY
8443209 12508935 THROTTLING COMPUTATIONAL UNITS ACCORDING TO PERFORMANCE SENSITIVITY
8443209 12508935 THROTTLING COMPUTATIONAL UNITS ACCORDING TO PERFORMANCE SENSITIVITY
8266569 12718594 IDENTIFICATION OF CRITICAL ENABLES USING MEA AND WAA METRICS
8266569 12718594 IDENTIFICATION OF CRITICAL ENABLES USING MEA AND WAA METRICS
8440516 12752487 METHOD OF FORMING A FIELD EFFECT TRANSISTOR
8440516 12752487 METHOD OF FORMING A FIELD EFFECT TRANSISTOR
8291146 12836731 SYSTEM AND METHOD FOR ACCESSING RESOURCES OF A PCI EXPRESS COMPLIANT DEVICE
8291146 12836731 SYSTEM AND METHOD FOR ACCESSING RESOURCES OF A PCI EXPRESS COMPLIANT DEVICE
8854381 12874134 PROCESSING UNIT THAT ENABLES ASYNCHRONOUS TASK DISPATCH
8854381 12874134 PROCESSING UNIT THAT ENABLES ASYNCHRONOUS TASK DISPATCH
8633725 12879993 SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION
8633725 12879993 SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION
8478942 12891027 METHOD AND APPARATUS FOR REDUCING PROCESSOR CACHE POLLUTION CAUSED BY AGGRESSIVE PREFETCHING
8478942 12891027 METHOD AND APPARATUS FOR REDUCING PROCESSOR CACHE POLLUTION CAUSED BY AGGRESSIVE PREFETCHING
8707117 12908630 METHODS AND APPARATUS TO TEST MULTI CLOCK DOMAIN DATA PATHS WITH A SHARED CAPTURE CLOCK SIGNAL
8707117 12908630 METHODS AND APPARATUS TO TEST MULTI CLOCK DOMAIN DATA PATHS WITH A SHARED CAPTURE CLOCK SIGNAL
8468547 12953367 METHOD AND SYSTEM FOR SYNCHRONIZING THREAD WAVEFRONT DATA AND EVENTS
8468547 12953367 METHOD AND SYSTEM FOR SYNCHRONIZING THREAD WAVEFRONT DATA AND EVENTS
8347250 12975668 METHOD AND APPARATUS FOR ADDRESSING AND IMPROVING HOLDS IN LOGIC NETWORKS
8347250 12975668 METHOD AND APPARATUS FOR ADDRESSING AND IMPROVING HOLDS IN LOGIC NETWORKS
8377761 13081575 SOI DEVICE HAVING A SUBSTRATE DIODE WITH PROCESS TOLERANT CONFIGURATION AND METHOD OF FORMING THE SOI DEVICE
8377761 13081575 SOI DEVICE HAVING A SUBSTRATE DIODE WITH PROCESS TOLERANT CONFIGURATION AND METHOD OF FORMING THE SOI DEVICE
8661300 13169977 ERROR DETECTION IN HIGH-SPEED ASYMMETRIC INTERFACES
9519943 13171979 Priority-Based Command Execution
9519943 13171979 Priority-Based Command Execution
8909840 13330482 DATA BUS INVERSION CODING
8909840 13330482 DATA BUS INVERSION CODING
8635566 13331172 PARITY ERROR DETECTION VERIFICATION
8635566 13331172 PARITY ERROR DETECTION VERIFICATION
9390554 13449410 OFF CHIP MEMORY FOR DISTRIBUTED TESSELLATION
8338961 13456968 SEMICONDUCTOR CHIP WITH REINFORCING THROUGH-SILICON-VIAS
8338961 13456968 SEMICONDUCTOR CHIP WITH REINFORCING THROUGH-SILICON-VIAS
8731046 13492281 SOFTWARE VIDEO TRANSCODER WITH GPU ACCELERATION
8731046 13492281 SOFTWARE VIDEO TRANSCODER WITH GPU ACCELERATION
9116809 13724879 Memory Heaps in a Memory Model for a Unified Computing System
9116809 13724879 Memory Heaps in a Memory Model for a Unified Computing System
9335999 13861083 ALLOCATING STORE QUEUE ENTRIES TO STORE INSTRUCTIONS FOR EARLY STORE-TO-LOAD FORWARDING
9335999 13861083 ALLOCATING STORE QUEUE ENTRIES TO STORE INSTRUCTIONS FOR EARLY STORE-TO-LOAD FORWARDING
8865527 13952392 LID ATTACH PROCESS
8865527 13952392 LID ATTACH PROCESS
None 14124771 COMPATIBILITY AND OPTIMIZATION OF WEB APPLICATIONS ACROSS INDEPENDENT APPLICATION STORES
9903913 14159247 SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION
9903913 14159247 SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION
9367891 14808113 REDUNDANCY METHOD AND APPARATUS FOR SHADER COLUMN REPAIR
9448930 14833850 MEMORY HEAPS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM
9448930 14833850 MEMORY HEAPS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM
10861122 15156658 REDUNDANCY METHOD AND APPARATUS FOR SHADER COLUMN REPAIR
10205956 15237134 TEXTURE COMPRESSION TECHNIQUES
None 15254466 MEMORY HEAPS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM
10078882 15346395 PRIORITY-BASED COMMAND EXECUTION
10078882 15346395 PRIORITY-BASED COMMAND EXECUTION
10324860 15695683 MEMORY HEAPS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM
10324860 15695683 MEMORY HEAPS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM
10970120 16019374 METHOD AND SYSTEM FOR OPPORTUNISTIC LOAD BALANCING IN NEURAL NETWORKS USING METADATA
10970120 16019374 METHOD AND SYSTEM FOR OPPORTUNISTIC LOAD BALANCING IN NEURAL NETWORKS USING METADATA
11119944 16443385 MEMORY POOLS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM
11119944 16443385 MEMORY POOLS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM
11841803 16456287 GPU CHIPLETS USING HIGH BANDWIDTH CROSSLINKS
11841803 16456287 GPU CHIPLETS USING HIGH BANDWIDTH CROSSLINKS
11169812 16584701 THROTTLING WHILE MANAGING UPSTREAM RESOURCES
11169812 16584701 THROTTLING WHILE MANAGING UPSTREAM RESOURCES
11386520 17113827 REDUNDANCY METHOD AND APPARATUS FOR SHADER COLUMN REPAIR
11880715 17222543 METHOD AND SYSTEM FOR OPPORTUNISTIC LOAD BALANCING IN NEURAL NETWORKS USING METADATA
11880715 17222543 METHOD AND SYSTEM FOR OPPORTUNISTIC LOAD BALANCING IN NEURAL NETWORKS USING METADATA
11741019 17471552 MEMORY POOLS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM
11741019 17471552 MEMORY POOLS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM
12032965 17519902 THROTTLING WHILE MANAGING UPSTREAM RESOURCES
12032965 17519902 THROTTLING WHILE MANAGING UPSTREAM RESOURCES
11948223 17862096 REDUNDANCY METHOD AND APPARATUS FOR SHADER COLUMN REPAIR
None 18265593 EFFICIENT MULLER C-ELEMENT IMPLEMENTATION FOR HIGH BIT-WIDTH ASYNCHRONOUS APPLICATIONS
None 18388602 GPU CHIPLETS USING HIGH BANDWIDTH CROSSLINKS
None 18455479 MEMORY POOLS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM
By PatenTrip
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