Advancing FPGA Innovations in Clock Distribution and Signal Processing
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| (Source: https://www.analog.com/media/en/company-csr/2023-esg-report.pdf) |
By PatentTrip
Analog Devices, Inc. acquired 66 U.S. patents from Flex Logix Technologies, Inc. in November 2024, enhancing its portfolio in Field Programmable Gate Arrays (FPGAs) and programmable logic technologies.
The patents span several critical areas, including:
Clock Distribution and Management: Efficient techniques for clock generation and distribution.
Logic Tile Architecture and Configurable Interconnects: Advanced designs for reconfigurable logic tiles and interconnect networks.
Programmable/Configurable Logic and Block Memory: Methods for dynamically configuring logic and memory components.
Multiply-Accumulate (MAC) Pipelines and Processing: Optimized MAC circuitry and pipelines for high-performance computing tasks.
FPGA-Specific Innovations: Modular FPGA designs and power-efficient operation techniques.
Advanced Signal and Data Processing: Applications such as fast Fourier transforms (FFT) and matrix operations.
Test and Error-Correction Techniques: Mechanisms for robust testing and fault recovery in programmable devices.
This acquisition solidifies Analog Devices' strategic position in the FPGA market, equipping it with advanced technologies to meet rising demands for sophisticated computing and signal processing solutions.
Below is the list of 66 U.S. patents acquired by Analog Devices from Flex Logix Technologies in November 2024 (Source: USPTO).
Patent Application Invention title
9240791 14712864 Clock Distribution Architecture for Logic Tiles of an Integrated Circuit and Method of Operation Thereof
9496876 14972553 CLOCK DISTRIBUTION ARCHITECTURE FOR LOGIC TILES OF AN INTEGRATED CIRCUIT AND METHOD OF OPERATION THEREOF
9543958 15015057 Multiplexer-Memory Cell Circuit, Layout Thereof and Method of Manufacturing Same
9503092 15041085 Mixed-Radix and/or Mixed-Mode Switch Matrix Architecture and Integrated Circuit, and Method of Operating Same
9786361 15213933 Programmable Decoupling Capacitance of Configurable Logic Circuitry and Method of Operating Same
9973194 15239958 Block Memory Layout and Architecture for Programmable Logic IC, and Method of Operating Same
9882568 15347045 Clock Distribution Architecture for Logic Tiles of an Integrated Circuit and Method of Operation Thereof
9793898 15347071 MIXED-RADIX AND/OR MIXED-MODE SWITCH MATRIX ARCHITECTURE AND INTEGRATED CIRCUIT, AND METHOD OF OPERATING SAME
9755651 15375284 MULTIPLEXER-MEMORY CELL CIRCUIT, LAYOUT THEREOF AND METHOD OF MANUFACTURING SAME
9906225 15375309 Integrated Circuit Including An Array of Logic Tiles, Each Logic Tile Including A Configurable Switch Interconnect Network
9941887 15691622 Multiplexer-Memory Cell Circuit, Layout Thereof and Method of Manufacturing Same
10176865 15726680 Programmable Decoupling Capacitance of Configurable Logic Circuitry and Method of Operating Same
10684975 15798224 One-Hot-Bit Multiplexer Control Circuitry and Technique
10250262 15898796 Integrated Circuit Including An Array of Logic Tiles, Each Logic Tile Including A Configurable Switch Interconnect Network
10411711 15975037 FPGA having a Virtual Array of Logic Tiles, and Method of Configuring and Operating Same
10680616 15978235 Block Memory Layout and Architecture for Programmable Logic IC, and Method of Operating Same
10348307 15996430 Clock Distribution and Generation Architecture for Logic Tiles of an Integrated Circuit and Method of Operating Same
10348308 16009656 Clock Architecture, including Clock Mesh Fabric, for FPGA, and Method of Operating Same
10411712 16042170 FPGA having Programmable Powered-Up/Powered-Down Logic Tiles, and Method of Configuring and Operating Same
10523209 16186882 Test Circuitry and Techniques for Logic Tiles of FPGA
10587269 16297596 INTEGRATED CIRCUIT INCLUDING AN ARRAY OF LOGIC TILES, EACH LOGIC TILE INCLUDING A CONFIGURABLE SWITCH INTERCONNECT NETWORK
10775433 16369809 Programmable/Configurable Logic Circuitry, Control Circuitry and Method of Dynamic Context Switching
10686447 16374735 Modular Field Programmable Gate Array, and Method of Configuring and Operating Same
10587271 16504248 Clock Distribution and Generation Architecture for Logic Tiles of an Integrated Circuit and Method of Operating Same
10686448 16504424 Clock Architecture, including Clock Mesh Fabric for FPGA, and Method of Operating Same
10693469 16545345 Multiplier-Accumulator Circuit, Logic Tile Architecture for Multiply-Accumulate, and IC including Logic Tile Array
10855284 16579766 PROCESS OF ROUTING TILE-TO-TILE INTERCONNECTS OF AN FPGA, AND METHOD OF MANUFACTURING AN FPGA
10867096 16659233 FPGA Implementing Partial Datapath Processing, and Method of Operating Same
10778228 16661217 Reconfigurable Data Processing Pipeline, and Method of Operating Same
10886922 16718619 Test Circuitry and Techniques for Logic Tiles of FPGA
11194585 16796111 Multiplier-Accumulator Circuitry having Processing Pipelines and Methods of Operating Same
11314504 16816164 Multiplier-Accumulator Processing Pipelines and Processing Component, and Methods of Operating Same
10972103 16887265 Multiplier-Accumulator Circuitry, and Processing Pipeline including Same
11288076 17019212 IC including Logic Tile, having Reconfigurable MAC Pipeline, and Reconfigurable Memory
11455368 17031631 MAC PROCESSING PIPELINE HAVING CONVERSION CIRCUITRY, AND METHODS OF OPERATING SAME
12015428 17074670 MAC Processing Pipeline using Filter Weights having Enhanced Dynamic Range, and Methods of Operating Same
11693625 17092175 Logarithmic Addition-Accumulator Circuitry, Processing Pipeline including Same, and Methods of Operation
11277135 17106124 Process of Routing Tile-to-Tile Interconnects of an FPGA, and Method of Manufacturing an FPGA
11960856 17140169 Multiplier-Accumulator Processing Pipeline using Filter Weights having Gaussian Floating Point Data Format
11323120 17140177 Test Circuitry and Techniques for Logic Tiles of FPGA
11442881 17212411 MAC Processing Pipelines, Circuitry to Control and Configure Same, and Methods of Operating Same
11476854 17219952 MULTIPLIER-ACCUMULATOR CIRCUITRY, AND PROCESSING PIPELINE INCLUDING SAME
11604645 17376415 MAC Processing Pipelines having Programmable Granularity, and Methods of Operating Same
None 17391082 Configurable MAC Pipelines for Finite-Impulse-Response Filtering, and Methods of Operating Same
None 17511798 Multiplier Circuit Array, MAC and MAC Pipeline including Same, and Methods of Configuring Same
11650824 17529421 Multiplier-Accumulator Circuitry having Processing Pipelines and Methods of Operating Same
None 17577454 MAC Processing Pipeline having Activation Circuitry, and Methods of Operating Same
11916551 17676123 Process of Routing Tile-to-Tile Interconnects of an FPGA, and Method of Manufacturing an FPGA
None 17683284 MAC Processing Pipelines, Circuitry to Configure Same, and Methods of Operating Same
11663016 17701749 IC INCLUDING LOGIC TILE, HAVING RECONFIGURABLE MAC PIPELINE, AND RECONFIGURABLE MEMORY
11893388 17719942 Multiplier-Accumulator Processing Pipelines and Processing Component, and Methods of Operating Same
11960886 17728829 Multiplier-Accumulator Processing Pipelines and Processing Component, and Methods of Operating Same
12008066 17816487 MAC Processing Pipeline having Conversion Circuitry, and Methods of Operating Same
None 17818924 Multiplier-Accumulator Circuitry, and Processing Pipeline including Same
11768790 17819958 MAC Processing Pipelines, Circuitry to Control and Configure Same, and Methods of Operating Same
12119819 18078033 Power-up Switch-Interconnect Configuration
None 18080673 MULTIPLY-ACCUMULATE WITH BROADCAST DATA
None 18088153 MULTIPLY-ACCUMULATE WITH VARIABLE FLOATING POINT PRECISION
None 18111846 BROADCAST DATA, SHARED WEIGHT MULTIPLY-ACCUMULATE
None 18144288 BROADCAST DATA MULTIPLY-ACCUMULATE WITH SHARED UNLOAD
None 18215993 Multiply-Accumulate Pipelines for Finite Impulse Response Filtering
None 18371228 Single-Weight-Multiple-Data Multiply-Accumulate with Winograd Layers
None 18371247 Single-Weight-Multiple-Data Matrix Multiply
None 18373453 Multiply-Accumulate with Configurable Conversion Between Normalized and Non-Normalized Floating-Point Formats
None 18373468 Multiply-Accumulate Engine with Non-Normalized Floating-Point Accumulator
None 18745051 Extreme-Throughput Fast-Fourier-Transform (FFT) Via Multi-Stage Tensor Processing
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